MQM8790-HS2F, NVIDIA® 40-Port 200G InfiniBand Data Center Switch, 40 x HDR QSFP56, Unmanaged, Mellanox Quantum™ Chip, P2C Airflow

Overcome link failures and achieves network recovery 5,000X faster than any software-based solution Overcome link failures and achieves network recovery 5,000X faster than any software-based solution Overcome link failures and achieves network recovery 5,000X faster than any software-based solution

Quickly resolve network issues due to specific port failures Quickly resolve network issues due to specific port failures Quickly resolve network issues due to specific port failures

SHIELD greatly reduces troubleshooting time SHIELD greatly reduces troubleshooting time SHIELD greatly reduces troubleshooting time

Support EDR, HDR and subsequent technologies Support EDR, HDR and subsequent technologies Support EDR, HDR and subsequent technologies

Deliver up to 16Tb/s of non-blocking bandwidth with extremely low latency Deliver up to 16Tb/s of non-blocking bandwidth with extremely low latency Deliver up to 16Tb/s of non-blocking bandwidth with extremely low latency

Scale-out data centers with HDR 200G infiniband Scale-out data centers with HDR 200G infiniband Scale-out data centers with HDR 200G infiniband

Support 200GBASE-SR4, CSR4, LX4, LR4, PLR4, PIR4, ER4 transceivers Support 200GBASE-SR4, CSR4, LX4, LR4, PLR4, PIR4, ER4 transceivers Support 200GBASE-SR4, CSR4, LX4, LR4, PLR4, PIR4, ER4 transceivers

Support 200G QSFP56 DAC and AOC cables  Support 200G QSFP56 DAC and AOC cables  Support 200G QSFP56 DAC and AOC cables 

Support 200G QSFP56 to 2x100G QSFP28 DAC and AOC cables Support 200G QSFP56 to 2x100G QSFP28 DAC and AOC cables Support 200G QSFP56 to 2x100G QSFP28 DAC and AOC cables

Support NVIDIA Mellanox Scalable Hierarchical Aggregation and Reduction Protocol (SHARP) Support NVIDIA Mellanox Scalable Hierarchical Aggregation and Reduction Protocol (SHARP) Support NVIDIA Mellanox Scalable Hierarchical Aggregation and Reduction Protocol (SHARP)

Offload collective communication operations from the CPU to the switch network by aggregating large data vectors at wire rate Offload collective communication operations from the CPU to the switch network by aggregating large data vectors at wire rate Offload collective communication operations from the CPU to the switch network by aggregating large data vectors at wire rate

Accelerate HPC, deep learning algorithm performance Accelerate HPC, deep learning algorithm performance Accelerate HPC, deep learning algorithm performance

Lowest latency for Inter-GPU communication across nodes Lowest latency for Inter-GPU communication across nodes Lowest latency for Inter-GPU communication across nodes

Build networks with MLNX-OS Build networks with MLNX-OS Build networks with MLNX-OS

Enable scaling to thousands of compute and storage nodesnodes  Enable scaling to thousands of compute and storage nodesnodes  Enable scaling to thousands of compute and storage nodesnodes 

Provide monitoring and provisioning capabilities Provide monitoring and provisioning capabilities Provide monitoring and provisioning capabilities