FS FPGA Smart NIC for Low Latency Networking
Updated at Oct 29th 20241 min read
FPGA is an acronym for Field Programmable Gate Array. FPGAs are semiconductor ICs where a large majority of the functionality inside the device can be changed; changed by the design engineer, changed during the PCB assembly process, or even changed after a product is deployed. FPGA SmartNICs are network adapter cards with hardware programmable accelerators and Ethernet connectivity that can accelerate infrastructure applications running on the host CPU. As today telecom operators face the challenges of network edge virtualization, traffic data path offloading to FPGA-based SmartNICs offer the ideal solution toward accelerating telco/cloud networks.
What are the Benefits of FPGA-based SmartNICs?
FPGAs are open, programmable hardware futureproofs edge sites such that hardware does not need to be replaced or upgraded as frequently. An FPGA on SmartNIC can be reprogrammed as needed, instead of replacing the whole card, if the application or use case changes. Reprogrammable FPGAs also provide the flexibility needed in a rapidly changing environment – ensuring assets are deployed efficiently and cost-effectively. Therefore, FPGA based SmartNICs provide unmatched scalability to enable communication service providers to easily handle large numbers of subscribers and devices at cost without significantly adding latency and power.
Cloud and multi-access edge computing (MEC) infrastructures require that equipment be optimized for carrier-level quality of experience, performance, and power at scale. With an FPGA, a network interface connects directly to the pins of the chip, which therefore offers very high bandwidth (as well as low latency) and better ability to scale for high throughput applications. By moving specific workloads onto a low-power, highly optimized adapter equipped with an FPGA-based flow processor, the host server can run more standard compute functions.
FPGA SmartNICs provide perfect balance for the network edge, with deterministic high performance on the one hand, and especially low space and power requirements on the other. They are also very effective in reducing latency. Deterministic low latency is a great advantage. By using an FPGA, it is feasible to achieve a latency around or below one milliseconds (ms), because FPGAs don’t rely on the operating system.
Superior Performance of FS FPGA NIC
FPGA SmartNICs provide perfect balance for the network edge, with deterministic high performance on the one hand, and especially low space and power requirements on the other.
The AG023R25A-1CP, Intel FPGA Based Ethernet Network Interface Card of FS natively offers industry-leading accelerations, such as hardware support for RoCE, overlay networks, stateless offload engines, flow control technologies such as PFC, DCQCN, and Go-Back-N retransmission, establishing end-to-end RDMA high-performance lossless networks. This resolves the deployment challenges of RDMA technology in high-performance computing, storage clusters, and other scenarios. Widely applied in data centers, cloud computing, storage, hyper-convergence, and other fields. Similarly, the on-board FPGA further increases flexibility by offloading the CPU of processes within custom applications.
The growing demand for security in the cloud and at the network edge requires both crypto and filters to be integrated for various types of data. The AG023R25A-1CP delivers security acceleration with IPSec tunnel offload that works together with additional overlay methods, such as VxLAN and NVGRE inline processing, freeing the CPU from intense security processing and thereby improving performance, providing ample bandwidth for line-speed communication on a single 100Gb port, designed to address security challenges for data center, networking and edge compute workloads, provides best-in-class performance and an unsurpassed feature set for virtualized telco and enterprise networks.

Conclusion
The exponential rise in network traffic in data centers increasingly burdens host server CPUs, which spend more of their time managing networking flows instead of running applications. These network-management tasks consume CPU cycles while increasing the cost for data-center operators. Incorporating an FPGA into a SmartNIC's design significantly enhances its data-plane flexibility and programmability. Replicating these pipelines by exploiting the large amount of hardware parallelism inherent in FPGAs improves megaflow performance enough to meet the high-performance, high-bandwidth, high-throughput needs of next-generation data-center architectures based on speedier Ethernet networks.