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800G & 1.6T Ethernet: Innovations and Challenges

HowardUpdated at Sep 11th 20231 min read

With the development of big data, 5G networks, cloud computing, and Internet of Things (IoT) technologies, the market's demand for higher bandwidth and data transfer rates is increasingly growing. In this article, the key challenges and innovations for 800G Ethernet and 1.6T Ethernet will be illustrated thoroughly.
What's the Timeline for 800G Ethernet & 1.6T Ethernet?
800G Ethernet is built upon the foundation laid by IEEE and OIF for 400G. The first 51.2T switch chip was released in 2022, supporting 64 ports of 800 Gb/s, and validation started on the initial batch of 800G optical modules.
In 2023, standard organizations released the first version of IEEE 802.3df and OIF 224 Gb/s standards, providing developers with a better understanding of how to build 800G and 1.6T systems using 112 Gb/s and 224 Gb/s channels. Over the next two years, standard organizations will finalize the physical layer standards and proceed with actual development and validation shortly.
Timeline for Upgrading to 800G and 1.6T Speeds
Challenges of Elevating to 800G Ethernet and 1.6T Ethernet:
How Can the Speed and Capacity of 800G Ethernet Be Increased?
The current implementation of 800G Ethernet utilizes 8 channels at 100Gbps per channel, doubling the PAM4 speed from 50Gbps (previous generation) to 100Gbps. The 800G transceiver with 200Gbps per channel is under development, which creates a significant challenge for 800G Ethernet.
Switch Silicon SerDes
Faster network switching chips are crucial for improving channel speeds in 800G Ethernet. Network switching chips enable low-latency switching between elements within the data center. The speed, quantity, and power of SerDes have also been increasing to support increased overall switching chip bandwidth.
SerDes speed has increased from 10 Gbit/sec to 112 Gbit/sec, and the number of SerDes around the chip has increased from 64 to 512 channels in the 51.2 Tbps generation. SerDes power consumption has become a significant part of the total system power. The next-generation switching chips will double the bandwidth again, as 102.4T switches will have 512 channels of 200 Gb/s SerDes. These silicon switches will support 800G and 1.6T on 224 Gb/s channels.
Pulse Amplitude Modulation
High-order modulation increases the number of bits per symbol or unit interval (UI) and provides a trade-off between channel bandwidth and signal amplitude. PAM4 modulation offers backward compatibility with previous generations of products. It provides a better signal-to-noise ratio (SNR) compared to higher modulation schemes, allowing for reduced forward error correction (FEC) overhead that contributes to latency. However, achieving PAM4 requires a better analog front-end (AFE) due to analog bandwidth limitations and advanced equalization implemented through innovative DSP schemes.
Currently, the industry may retain the versatility of PAM4 in 800G Ethernet or 1.6T Ethernet while exploring alternative methods for high-speed data integrity maintenance. However, future iterations may employ higher modulation schemes such as PAM6 or PAM8.
PAM4 signals have smaller eye heights, requiring tighter design margins for noise and jitter
How to Reduce Bit Error Rate in 800G Ethernet Network?
In most high-speed data standards, fine-tuning equalizers in transmitters and receivers ensures that the signals transmitted through the channel can be interpreted at the other end, compensating for signal attenuation. However, as faster speeds push the physical limits further, more sophisticated methods are required. One such solution is forward error correction (FEC).
Forward error correction involves transmitting redundant data to assist the receiver in reconstructing the signal with damaged bits. FEC algorithms can recover data frames from random errors but encounter burst errors when an entire frame is lost. Each FEC architecture has trade-offs and advantages regarding coding gain, overhead, latency, and power efficiency. In a 224 Gb/s system, more complex FEC algorithms are used to minimize burst errors.
Different FEC Architectures have Varying Tradeoffs
FEC Schemes
Example Options
Coding Gainover KP FEC
Overhead
Latency
Power/Area
End-to-end
RS (576,514,31)
-1.5 dB more
6% more
Incremental increase
Incremental increase
Segmented
KP and FECo
FECo dominant
FECo dominant
Significant increase
Significant increase
Concatenated
KP+BCH/Hamming
~0.5-1.5 dB
3% -6% more
Incremental increase
Incremental increase
How to Enhance Power Efficiency in 800G Ethernet Network?
The most challenging issue 800G Ethernet or 1.6T Ethernet data centers face is power consumption. The power consumption of optical modules has been increasing with each generation. As optical module designs mature, they become more efficient, decreasing power consumption per bit.
However, due to the average of 50,000 optical modules in each data center, the overall power consumption of the modules is still a concern. Co-packaged optical devices can reduce the power consumption per module by integrating optoelectronic conversion within the package. However, cooling requirements remain a challenge in this approach.
In 800G Ethernet, a key innovation of co-packaged optical devices is to move the optical components close enough to the bare die of the Switch ASIC to eliminate the need for an additional DSP (as shown in the diagram below).
Pluggable and Co-packaged Optics
FS 800G Ethernet Transceivers
To cater to the current development prospects of high-performance computing, FS provides a series of 800G Ethernet transceivers. Our 800G Ethernet transceivers are engineered and tested for reliability to meet the ever-changing needs of modern networks. The following are FS 800G Ethernet transceivers:
FS P/N
Power Consumption
Connector
Distance
≤13W
MTP/MPO-16
50m
≤16.5W
MTP/MPO-16
500m
≤18W
MTP/MPO-16
10km
≤14W
Dual MTP/MPO-12
50m
≤16.5W
Dual MTP/MPO-12
500m
≤16.5W
Dual LC Duplex
2km
≤16.5W
MTP/MPO-16
10km
≤16.5W
Dual MTP/MPO-12
10km
≤18W
Dual LC Duplex
10km
FS 1.6T DAC Cable
In addition to 800G transceivers, FS offers innovative 1.6T OSFP DAC cables, designed with 8x200G PAM4 to deliver ultra-high bandwidth. These cables feature superior mechanical durability and excellent shielding to minimize crosstalk. With reliable signal integrity (SI) and ultra-low power consumption of 0.1W, the FS 1.6T OSFP224 DAC cables meet the rapidly growing traffic and data processing demands of hyperscale data centers and HPC networks while reducing costs.
Currently, numerous hyperscale data center operators are preparing for future deployment of the GB200 NVL72 system. FS has launched an industry-leading innovation, called the 1.6T OSFP DAC cable, which provides outstanding performance for the next-generation GB200 NVL72 architecture.
Conclusion
With advanced technology and superior performance, FS is your trusted partner for the next generation of networking solutions. 800G Ethernet and 1.6T Ethernet will be essential in the future, delivering unparalleled high-speed connectivity and expanded bandwidth. In the coming years, higher capacities, faster speeds, and significant efficiency improvements will be necessary. Under the GB200 NVL72 architecture, 1.6T transceivers and cables can better meet these demands and boost Ethernet. Contact FS today to upgrade your network to 800G and stay ahead in the digital era.